What worked best for me across several different MCUs and ready-to-use FT81x/BT81x modules are 74LVC2G17 / 74VHC1G12 buffers and 56R series resistors.

The slew rate / drive strength settings are a bit counter intuitive.
ST for example has "Maximum output speed" settings for the STM32 with levels "Low" / "Medium" / "High" and "Very High".
But using "Very High" is not necessarily the correct idea.
Ideally you match the output to your transmission line impedance.

Analog voodoo in digital transmissions. :-)

For very long I had the luxury of getting away with ignoring the issue.
First my controllers were on the slower side and did not have any settings while driving the lines rather strong,
then I had an issue with a controller having too weak outputs at 3.3V, so I added external buffers as drivers.

Next I learned that my library was not playing well with the Teensy 4 which uses a RT1062, the usuable SPI clock was surprisingly low.
As the Teensy 4 is typically used with Arduino, the settings are made by the classes.
And when I figured out how to change the settings in order to configure for a higher speed, I learned that by default the pins
already were configured for the highest setting.
Using a lower setting worked better - or raising the series resistance.

Hello,

Thank you for the update.

In cases where the SPI connection is long and there is no possibility to shorten it significantly, we would normally suggest adjusting the slew rate and drive strength characteristics of the MCU SPI port to help improve transmission quality. But please do keep us updated with how your testing goes.

Best Regards,
BRT Community

The SPI clock is actually 10 MHz, not 12 as previously stated.  That seemed reasonable, and I was considering increasing it since the FT813 can support up to 30 MHz.  However, due to the mechanicals of the system, the ribbon cable connecting the main board to the display looks like it's 16 to 18 inches.  I don't know what this translates to as far as a max SPI clock speed, but maybe 10 MHz is pushing the envelope.

I was going to run a test with a lower clock speed, but identified a separate problem/bug in the application firmware.  The code that initiates the SPI transaction to get touch tag was not checking the return code from the SPI library call that executes the transaction; it just set the flag indicating that a tag had been read and thus no longer available to read.  The application was locking up on a particular screen, and when it stopped responding to touch, the interrupt was firing, the flags indicated a new touch tag was available, but there was no SPI transaction to read the tag, even though that code is executed unconditionally.  This indicated a failure in the SPI library call (this is on an NXP RT1064, by the way).  I moved the line of code that cleared the touch tag available flag to the point where the call had to have succeeded, which will force a retry on failure.  I could not reproduce the lockup scenario after making this change.

What's peculiar about this is that I was also no longer able to reproduce the 300 ms gap when refreshing the main screen, but that has nothing to do with touch tags.  I'm wondering if moving around the cable to check length affected performance somehow.  These issues do appear to be related to the SPI port at the micro.

With regard to the interrupt handler, it does not include any SPI transactions.  The concern was that an interrupt could occur in the middle of sending commands to the coprocessor in preparation for updating the display.  The interrupt handler just sets a flag indicating that an interrupt has occurred, and the application idle loop picks up on that and reads the interrupt flags when the command coprocessor is idle.

I am going to continue to test, and will post logic analyzer logs along with images if I see issues.

Please attach logfile from your logic-analyzer, there really is not much to see in these images.
Not that I am expecting to see anything at 12MHz, but there is not really much to analyze with these images.

Hello,

On the programmers guide point, this is currently going through the final review stages and we hope to have it released shortly.

I will follow up with the R&D team for your other queries.

Best Regards,
BRT Community

Hello,

Thank you for the update and the details.

I had a quick discussion with the R&D team concerning the operation of the of REG_INT_FLAGS, REG_INT_MASK, and the INT_N pin in general. After viewing the associated microcode I can note that the  REG_INT_FLAGS register is always set by hardware, however, the INT_N pin is only asserted to low when the corresponding bit of REG_INT_MASK is enabled. In this case it may be possible to some values from the REG_INT_FLAGS register that hadn't previously been set in the masking stage.

However, in believe in this case that the 0x4A you are reading from the register should likely be 0x25 (SWAP, TAG, FIFO empty). It is possible that there may be a hardware related issue causing this, one approach would be to test the register reads using a slower SPI clock rate as Rudolph has suggested. But, I would be interested to know in the first instance if the ISR has any bearing on the behaviour you are seeing. Would it be possible to test the ISR where you only perform a read of the REG_INT_FLAGS register on the INT_N pin toggling? and do not service the routine or send any new commands to EVE otherwise. I'm curious to see if the 0x4A register read still occurs in this instance.

Best Regards,
BRT Community

Any ETA on an updated BT82x programming guide?

A few answers to the more crucial questions I posted would be very nice beforehand.
Like how REG_LVDSTX_PLLCFG actually works - if the guide is wrong there and I am not using the register incorrectly...


And I have a new question.
Is there a way to check if rendering of a display list is done?
Well yes, I could read REG_RE_RENDERS and check for a change.
But this takes a bit of caution and requires to not into a deadlock.
Or I guess using CMD_GRAPHICSFINISH could work, reading REG_CMDB_SPACE after this should indicate that the co-processor is waiting for the render engine to finish.
Hmm, sounds like a plan, I maybe should always end the BT82x display list with CMD_GRAPHICSFINISH and not send a new display list when the co-processor is still busy.

Well yes, there might be other things to do for the co-processor while the render-engine is busy, like loading assets or using CMD_TEXTDIM, in that case ending the display-list with CMD_GRAPHICSFINISH might be a bit inefficent, perhaps, especially when the render engine needs a bit more time than usual.

Interrupts are configured by writing 0x05 to REG_INT_MASK, then writing a 1 to REG_INT_EN.

Logic analyzer traces are attached.  I don't have the greatest logic analyzer, so the clock appears a little inconsistent (clock speed is 12 MHz).  The clock line is the top line with MISO below.  This is the pattern on each occurrence of invalid flags.  There is also a trace of a series of 100 ms updates showing the 300 ms gap when the flags are incorrect.

The screen manager is very basic; there is no screen stack involved.  It includes an active screen variable that gets updated based on user input on each screen.  The touch tag handler within each screen can update the active screen variable as necessary.  The active screen value directs touch tags received to the user input handler for the screen currently displayed.  It may be that I need a more reliable way to determine that a screen update is actually complete.  Accessing the SPI bus to read interrupt flags or touch tags is blocked when the application starts writing out screen commands to the command coprocessor, and is then allowed after the swap interrupt occurs.  The 300 ms timeout is a hack I had included early on, and needs to be removed and replaced with a better-thought out recovery mechanism if something goes wrong.

I can get with the hardware guy to discuss layout and pin configuration to see if there could be any issues with reflection or other hardware-related issue.

With some further testing I can check off a few questions:

*The offset of REG_SPI_WIDTH is 0x188 (the programming manual (v2.1) incorrectly states it is 0x180)
*You can write to the register using just 8 bits despite the manual indicating it's a 32 bit register
*This does appear to take effect once CS is released

So I really only have one outstanding question which is whether or not the SPI mode can be switched from normal to dual/quad at any time or if there is only a certain window during which this can take place.

I'm having trouble getting dual SPI mode to work. I've got some test code stood up that first reads REG_SPI_WIDTH which returns 0 as expected. I then try to set bit 0 to 1 using a write command, but this does not seem to take. I've verified this two ways:

* Read REG_SPI_WIDTH again to see if the new setting is in effect (this always returns 0) reading in both normal and dual SPI modes
* Read chip ID to see if it can be read back. No matter what I get the correct ID reading it in normal mode which suggests the setting has not taken effect

When exactly does the change take effect? I assume after CS is released? Does this register need to be handled as 32 bits or 8 bits? What is the correct offset for REG_SPI_WIDTH? 0x188?

The following code example is for the ESP-IDF.


#define REG_SPI_WIDTH        0x00302188
#define MEM_WRITE 0x80

static const uint8_t rxBits = 32;
trans.addr = REG_SPI_WIDTH;
trans.length = 0;
trans.rxlength = rxBits + dummyBits; //default to same as length
trans.tx_buffer = NULL;
trans.rx_buffer = rxBuf;
ret = spi_device_polling_transmit(EVE_spi_device, &trans);
assert(ret==ESP_OK);

uint32_t regSPI = 0;
memcpy(&regSPI, rxBuf+1, 4);
printf("%x\n", regSPI);

// write new register value, I've considered MSB and LSB encoding for these with no observed differences
trans.tx_data[0] = 0x1;
trans.tx_data[1] = 0x0;
trans.tx_data[2] = 0x0;
trans.tx_data[3] = 0x0;

trans.addr = REG_SPI_WIDTH | (MEM_WRITE << 16);
trans.length = rxBits;
trans.rxlength = 0;
trans.tx_buffer = NULL;
trans.rx_buffer = NULL;
trans.flags = SPI_TRANS_USE_TXDATA;
ret = spi_device_polling_transmit(EVE_spi_device, &trans);
assert(ret==ESP_OK);

trans.addr = REG_SPI_WIDTH;
trans.length = 0;
trans.rxlength = rxBits + dummyBits;
trans.tx_buffer = NULL;
trans.rx_buffer = rxBuf;
trans.flags = 0;
//trans.flags = SPI_TRANS_MODE_DIO;
ret = spi_device_polling_transmit(EVE_spi_device, &trans);
assert(ret==ESP_OK);

memcpy(&regSPI, rxBuf+1, 4);
printf("%x\n", regSPI);


This is occurring after initialization and after fast flash has been enabled.

Edit: I did another test where I switched to dual SPI shortly after the check of REG_CPU_RESET during initialization and this seems to have worked. Is it not possible to switch SPI modes at some point?