I just added the functions for CMD_RESTORECONTEXT and CMD_SAVECONTEXT.
And I do not get it, what was the point of adding these as commands to the co-processor?

SAVE_CONTEXT and RESTORE_CONTEXT are display-list commands that were introduced with the FT800, IDs 0x22 and 0x23.
And executing these with the co-processor, like the rest of the display-list commands, never was an issue.

So instead of having the co-processor just copy over the commands to the display-list it now has to exectute the
command to write the same values to the display-list.
This really strikes me as weird.
And then these were the only display-list commands that got that privilege to be elevated to co-processor commands.

I just implemented CMD_RESULT and had an idea.

The register region has room for over 2100 registers in the BT820.
Documented are 155 right now and regardless of how many register are undocumented, it should be highly unlikely that
there are not plenty of unused slots.

Can we please reserve a bunch and name them like REG_USER0 to REG_USER9?

Why?
Because CMD_RESULT(REG_USER0) would be nicer than needing to find places in the memory map over and over again.

Hello,

Thank you for the update!

I'm glad to hear that adjusting the REG_AH_HCYCLE_MAX registers has helped in this instance.
Please let us know if you have any further questions.

Best Regards,
BRT Community

Quote from: Rudolph on March 31, 2025, 04:24:03 PM
I just went back to this and added:

EVE_memWrite32(REG_AH_HCYCLE_MAX, EVE_HCYCLE + 500);

And with this I have it up and running on my RVT101H right now with more buttons and the gradient.

Forgive me for the late reply, but I did not receive a notification.
I had some time today to make some tests, and enabling the adaptive framerate as well as adding the line you mentioned did work very well. Thanks a lot, that's going to help a great deal going forward.

I also noticed a typo in my own code, which would explain why I read 0 for underrun; after fixing that, the example I posted before gave me a ~72000 value.

The picture is nice and stable, yes, I started to implement the new commands for the BT820. 

But I currently have an issue that I can not explain.
First I noticed that I need to place additional VERTEX_FORMAT(0) in my display list, somehow the setting is not persistent.
Then I noticed that the back-to-back CMD_TEXT in the snippet I am using with CMD_APPEND no longer work, only the first line is displayed.
And when checking with the logic analyzer I found that a single CMD_TEXT is keeping the command-co-pro busy for an unusual amount of time, like there is some issue.
When I interleave the CMD_TEXT with COLOR_RGB then all the lines are displayed, the co-pro still is busy with this for quite a while though.

Choosing the less complicated CMD_NUMBER I get the same:

EVE_cmd_dlstart();
EVE_color_rgb(BLACK);
EVE_cmd_number(10, 515, 26, 0, 12345);
EVE_cmd_number(10, 500, 26, 0, 12345);
EVE_execute_cmd();

Followed by:
num_dl_static = EVE_memRead16(REG_CMD_DL);
EVE_cmd_memcpy(MEM_DL_STATIC, EVE_RAM_DL, num_dl_static);

The result right now is that the second line is not completely displayed.
When I switch the order of the lines, the other one gets incorrectly displayed.

When I throw in an extra EVE_color_rgb(BLACK); between the two CMD_NUMBER, then both lines are displayed.
When I use a NOP one of the lines still get corrupted.

The resulting sequence for EVE_cmd_number(10, 515, 26, 0, 12345); is:
0xff 0x01 0x00 0x00 - write + REG_CMDB_WRITE
0x2a 0xff 0xff 0xff - CMD_NUMBER
0x0a 0x00 0x03 0x02 - x = 10, y = 515
0x1a 0x00 0x00 0x00 - font = 26, options = 0
0x39 0x30 0x00 0x00 - number = 12345

I still need to read out the resulting display list snippet and analyze it, but right now I do not see anything wrong with my code.

Hmm, I added the lines with x=110 to the main display list and also made the list use separate commands instead of using DMA,
the two lines are displayed just fine.
Then I checked my implementation of CMD_APPEND, nothing there, changed the target address for the snippet, no change.

Looks like the co-processor does not like to put commands in a display list anymore that is not meant to be displayed on it's own?
There is no CLEAR_COLOR_RGB or CLEAR for the snippet, as this is in the main display list.


Edit: I just modified my code to use CMD_NEWLIST/CMD_ENDLIST/CMD_CALLLIST which just stores the co-processor command instead of executing them.
And this works just fine, when executed in the context of the display list, both lines for CMD_NUMBER are displayed correctly.

After restoring the rest of my original code everything is executed as it should, I even can remove the two extra VERTEX_FORMAT(0) lines that
were necessary before.
I noticed in ESE that both CMD_NUMBER and CMD_TEXT switch to use SAVE_CONTEXT / VERTEX_FORMAT(2) when going beyond 511 on the B817/BT818.
And with the BT820 SAVE_CONTEXT is replaced with REGION.
Oh wait, that is the issue, the destination in REGION is absolute, not relative, so with CMD_APPEND destinations are pointing to the wrong address in the display list.

At least there is a workaround, although it is exclusive to BT817/BT818/BT820.
Makes me again wonder why VERTEX_FORMAT(0) is not just the default.

Additionally I found that CMD_NEWLIST is not finishing on it's own, REG_CMDB_SPACE never indicates that the FIFO is empty.
Only after I removed the busy check things worked.
This behaviour is not documented and something I should try on the BT817.

Hi Rudolph,

Congratulations on getting the BT810B up and running on your board !
Glad to hear that you found the cause of the issue with the contact side on the touch connector already and that it's working well now.

Is your picture nice and stable now on the display too?
We'll check the definitions of the REG_LVDSTX_PLLCFG in the guide.

Best Regards, BRT Community

How do I use the touch engine?
As far as I understand it, setting bit 6 in SETBOOTCFG should be enough, this should enable the touch system and
during boot the touch system should do an auto-discovery to determine the touch controller connected.

My LCD does have a FT5316 and after connecting it to the VM820C it does nothing at all.
Reading REG_TOUCH_CONFIG returns 0x00000000, writing 0 or 0x381 does nothing either.

I can not calibrate and reading REG_TOUCH_RAW_XY returns 0xFFFFFFFF.

It should not be necessary to setup CTP_SCL/GPIO5, CPT_SDA/GPIO6, CTP_INT/GPIO7 or CTP_RST/GPIO8 in order to use the touch engine.
But then I can not find how to actually set this up anyways, how to configure them for alternate function or GPIO.

Edit: I soldered pins and to the FFC adapter I am using for the touch controller and looking at SCL, SDA and Reset with the logic analyzer.
And while the pins wiggle like expected for their function, the touch controller does not seem to answer.

What is odd though, when I write 0x381UL to REG_TOUCH_CONFIG to setup a FocalTech device, the lines are just dead.
SCL is Low - really odd for an open collector ouput with pullup-resistor, SDA and Reset are high.

When I write 0x380UL to REG_TOUCH_CONFIG, which should not do much according to the register description,
apparently auto discovery is triggered, Reset is pulled low, then there is a pause and then there is one or two byte transfers on SCL/SDA.
Same thing happens when not writing to REG_TOUCH_CONFIG or when writing 0.

Oddly I also see 311ms periods with SCL just low like this, even when I disconnect the CTP.

Maybe my touch controller is toast, but what the BT820 does is not looking correct either.

Looks like I need to check the touch controller with an Arduino, there was some I2C scan sketch somewhere.
Edit: I did just that, I have an Arduino UNO running at 3.3V with 4k7 pullup resistors to 3.3V scan the I2C right now, connected to the CTP of the display as written on it's FFC cable: 1 = GND, 2 = SDA, 3 = SCL, 7 = VDD - and nothing is found.
Strange.


Edit: I found the issue, I do have working touch now. 

The connector on the 10pin FFC adapter board I am using looks like is contacting on both sides of the cable,
but it definately is only contacting on the bottom side.
The cable for the CTP has the contacts on the top side...

Have two fotos to celebrate. :-)
Yes, I noticed that the backlight is a bit dim, but I can't control it by software and only set it to 20mA, maybe I'll add another resistor in parallel later.


Edit: I just put up a repository with the information from reverse engineering this display adapter: https://github.com/RudolphRiedel/PCB800182_LCD_Adapter

And I am celebrating the first stable output on a LCD from the BT820! 

I am still having a weird timing issue, the output of the 1024 x 600 image is only to 3/4 of the width of the screen.
And nothing I did to the timing parameters so far made that smaller or wider, it only changes from stable to chaos.

Edit:
And now I have the image stretched across the complete display area. 

Looks like my PixelClock was too low.
With some trial and error I ended up with NS = 7 and DIV = 4 - REG_LVDSTX_PLLCFG = 0x00300874
NS = 7 and DIV = 2 is not working.
NS = 7 and DIV = 3 to DIV = F is working, although it starts to flicker at DIV = B.
NS = 8 and DIV = F is not working, although this should only be a little higher than NS = 7 and DIV = F.

My guess is that the description of REG_LVDSTX_PLLCFG is not correct.
But I can not measure the resulting pixel clock directly, I do not have an oscilloscope here.

I am getting closer,but the output on my LCD still is corrupted.
But at least I can see that there is something going on now, I am using CMD_LOGO and there is some movement in the chaos for a couple of seconds.

I found that my function of calculating the value for REG_LVDSTX_PLLCFG was completely broken.
But after fixing it, it still does not work.
As it turns out, the description for REG_LVDSTX_PLLCFG in the programming guide is wrong.
The reset default value is 0x00300877 - and that is correctly stated.
"Table 18 – LVDSTX Clock Configuration" can not be correct though, first indication is that 15 and 8 are not the default values.

And in the datasheet I finally found this:

Quote
4.12.2 Phase Locked Loop
There are 4 Phase Locked Loops (PLLs) inside the chip; the system PLL (PLL1), LVDSPLL (PLL2), DDRPLL
(PLL3) and the DDR PHYPLL (PLL4)
The system PLL receives the input clock from the oscillator and produce both the system clock and the
LVDSTX clock.
The LVDS PLL takes the input clock from the LVDSTX clock and generates the LVDS fast clock.
The DDRPLL and the DDR PHYPLL are used to generate clock for the DDR interface.

And while this not quite cleary written, it shows that that input for the LVDSPLL (PLL2) is not the Oscillator with 38.4MHz,
but the system clock that is generated by the system PLL (PLL1) and which defaults to 72MHz.

So when I tried to use NS = 8 and CLKDIV = 5 in order to setup the LVDSTX clock to 51.2MHz, I was setting it up to 96MHz instead,
which is out of spec for the LCD I have.

The default value of 0x00300877 should result in a pixel clock of 63MHz, however LVDSPLL_CK is configured incorrectly to 0b01, if I am understanding the
programming guide correctly, that would be for a CTLCLK range of 200MHz to 400MHz, NS = 7 and input = 72MHz results in 504MHz though.
So a valid default value should have been 0x00301077.

And with 72MHz as input for the LVDSTX PLL I can not set the clock to 51.2MHz - pretty close to 51.43MHz though.

There is no maximum range given for either SYSPLL_CKS or LVDSPLL_CK, according to REG_SYS_CFG and REG_LVDS_PLLCFG it might be
400MHz to 800MHz for SYSPLL_CKS and 200MHz to 800MHz for LVDSPLL_CK.
That would put the valid range for NS of system clock to a range of 11 to 20 while 72MHz might be the the highest Systemclock allowed.

And with 72MHz system clock the allowed range for NS of the LVDSTX PLL would be 3 to 12.
But well, the allowed range for the system clock might be 36MHz to 72MHz.

If I am correct on this, please provide updated versions of both the DS_BT820 and BRT_AN_086_BT82X-Series-Programming-Guide
with more and accurate information.

Oh yes, I also found BRT_AN_092-BT820-Hardware-Design-Example, unfortunately there is nothing in there on setting up LVDSTX.

Another source of information could have been EVE Screen Editor.
However, v5.0.0 only shows a fraction of the the registers in RAM_REG and there are no built-in settings for connecting to a 1024x600 LCD.

Hi,
Yes, RGB565 is a commonly used 16-bit image format, but it does result in some loss of color information — especially for neutral tones like grayscale.
This is because RGB565 allocates only 5 bits for red and blue, and 6 bits for green. The imbalance in bit allocation can cause color distortion, which may lead to grayscale areas appearing bluish on the display.
If you want to preserve better color fidelity, we recommend using the ASTC compression format.
You can use our EVE Asset Builder tool to convert images into ASTC format.
For example, using 8×8 ASTC compression typically provides visually good quality while producing a smaller data size than RGB565.


Best Regards, BRT Community