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void configure_lvds(void)
{
EVE_memWrite32(REG_RE_DEST, EVE_SWAPCHAIN_0);
EVE_memWrite32(REG_RE_FORMAT, EVE_ARGB8);
EVE_memWrite32(REG_RE_W, EVE_HSIZE);
EVE_memWrite32(REG_RE_H, EVE_VSIZE);
EVE_memWrite32(REG_DISP, 1);
EVE_memWrite32(REG_LVDSTX_PLLCFG, setlvdspll_value(0, PLL_LOCK_PERIOD, 1, 10, 7)); /* 38.4 MHz * 10 / 8 = 48MHz */
EVE_memWrite32(REG_LVDSTX_EN, LVDS_CH0_EN);
EVE_memWrite32(REG_SC0_RESET, 1);
EVE_memWrite32(REG_SC0_SIZE, 2);
EVE_memWrite32(REG_SC0_PTR0, 10 << 20);
EVE_memWrite32(REG_SC0_PTR1, 20 << 20);
// EVE_memWrite32(REG_SC1_SIZE, 2);
// EVE_memWrite32(REG_SC1_PTR0, SC1_PTR0_STARTADDR);
// EVE_memWrite32(REG_SC1_PTR1, SC1_PTR1_STARTADDR);
// EVE_memWrite32(REG_SC2_SIZE, 2);
// EVE_memWrite32(REG_SC2_PTR0, SC2_PTR0_STARTADDR);
// EVE_memWrite32(REG_SC2_PTR1, SC2_PTR1_STARTADDR);
EVE_memWrite32(REG_SO_EN, 0);
EVE_memWrite32(REG_SO_MODE, EVE_SO_MODE_2);
EVE_memWrite32(REG_SO_SOURCE, EVE_SWAPCHAIN_0);
EVE_memWrite32(REG_SO_FORMAT, EVE_ARGB8);
EVE_memWrite32(REG_SO_EN, 1UL); /* enable scanout */
DELAY_MS(10);
}
Quote
The transactions are word based, i.e., the data width must be in blocks of 32 bit when accessing the
registers and the DDR memory of the BT820. Addressing to the registers and the DDR memory must also
be word aligned, i.e., the last two bits of the received address are ignored.
Quote
The write data is expected to be in blocks of 32-bit. Any incomplete data is discarded when SS_N deactivates.
Quote from: TreeOone on March 31, 2025, 07:57:34 PM
I was not aware of pixel engine's limitations.
Quote
Rudolph, your library is great. Unfortunately for me, it is heavily dependent on SPI communication, which is not ideal for me, because I am using QSPI, which on STM32 works a little bit different, so I had to rewrite all functions in EVE_commands.c.